1. Field of the Disclosure
The present embodiments relate to semiconductor wafer processing equipment tools, and more particularly, edge ring assemblies used in plasma process chambers.
2. Description of the Related Art
Despite advances in the pursuit of across-wafer uniformity, etch behavior at the edge and extreme edge regions of the wafer continues to be a challenge. At least 10% of the die are impacted in this region of the wafer and the economic impact can be especially significant considering the increasing cost-per-die. Far edge effects (e.g. at 140-150 mm along a radius of a 300 mm wafer) with an edge exclusion of about 1-5 mm is an active focus of current manufacturing efforts for achieving within wafer uniformity.
Since most processes tend to be transport driven, etch performance depends on plasma composition above a specific area of the wafer, and in any plasma source there will inherently be some non-uniformity and effects from the chamber walls. Plasma species composition of neutrals and ions at the edge of the wafer tends to be different as compared to the center of wafer due to discontinuities resulting from the ‘finite wafer size’ that causes both electrical and chemical discontinuities. Coupled with gradients in neutral flux, the etch behavior at the extreme wafer edge can be quite different than the rest of the wafer.
Voltage gradients are created at the wafer edge due to the change from a biased surface to a grounded or floating surface. Along with different electrical properties between the wafer and the chamber materials (specifically edge ring), the result is sheath bending and off-normal ion flux and ion focusing to the wafer. This causes undesirable effects on etch features that manifest as non-uniformity either through feature tilting and/or critical dimension (CD) variation.
Currently dielectric edge rings with varying degree of conductivity in reactive ion etch chambers (e.g. Kiyo® series process chambers manufactured by Lam Research Corporation) are used to prevent exposing the electrostatic chuck (ESC) to the processing plasma and inherently give rise to electrical discontinuity near the wafer edge due to change in material properties. An additional tuning knob does not exist for mitigating ion-focusing and ion trajectories caused by bending of the plasma sheath due to this discontinuity in electrical properties and thus the issues of feature tilting as well as CD non-uniformities persist.
It is in this context that embodiments of the disclosures arise.